1. Field of the Invention
This invention relates generally to the manufacture of semiconductor devices and more specifically to developing test programs for semiconductor devices.
2. Related Art
Semiconductor devices are generally tested at least once during their manufacture. Such tests are performed by an automated test system that can generate large numbers of stimulus signals and measure large numbers of response signals. The test system has multiple instruments that can generate various types of signals that may occur within a device under test as it operates. Similarly, the instruments can measure the various types of signals that may be generated by the device.
For example, many semiconductor devices are fabricated today as a “system on a chip” (SoC) or a “system in a package” (SiP) that contain sub-circuits, sometimes called “cores” or “functional blocks,” that collectively perform multiple types of operation that may be performed by an electronic device. As a specific example, a chip that may be used in cellular telephone may have cores that send and receive radio frequency (RF) signals. Other cores may control the RF circuitry and yet another core may act as a general purpose processor that can be programmed to run applications. To fully test such an SoC or SiP device, a test system may have instruments that generate and measure RF signals and instruments that generate and measure digital signals such as may be processed within the control core and processor core. A test system will also have instruments that can generate and measure other signals of the types that may occur within an operating semiconductor device, such as voltage and current signals of the type that may be applied by a power supply during device operation, or signal that may be read from a sensor. These instruments collectively provide resources for performing tests.
As devices have gotten more complex, the complexity of test systems required to test the devices has increased. Additionally, more time is required to create test plans and to perform the tests, creating a concern for device manufacturers over the cost of test. One way in which this concern is addressed is through the use of concurrent test processes. A test process may be made concurrent for a particular device by testing multiple cores, or other regions of the device, in parallel. Separate tests or groups of tests, which are sometimes called test blocks, may be developed for each of these regions. For such testing to be effective, execution of one test block should not affect operation of any other part of a device that is being concurrently tested by another test block. Accordingly, a difficulty in making a concurrent test plan is identifying an appropriate test “flow” in which all test blocks are eventually executed, but that includes appropriate test blocks being executed together to save more test time.
A further difficulty in making a current test plan is ensuring that the test system to conduct the test has enough resources to generate and measure all of the signals required for all the test points concurrently being used for a test. Each location of a device at which a test signal is to be applied or measured is sometimes called a “pin.” One aspect of making a concurrent plan is ensuring that the test system has enough instruments to provide the required resources at each pin involved in a test. Frequently, instruments are sold separately from test systems such that the test system can be configured for testing a specific device by installing instruments to provide required resources. As more test blocks are tested concurrently, more instruments may be required. In making a concurrent test plan, a tradeoff may be made between the number of blocks tested concurrently and the number of instruments in the test system configuration.
Another consideration in establishing a concurrent test plan is ensuring that signals from the instruments inside the test system are routed to a pin. In many test systems, this routing between pins and instruments is performed with a device interface board (DIB), which may be specially designed for each type of device to be tested. A test system has a predefined number of access points, each of which may be referred to as a channel. Each channel may act as an input, an output or both for one signal for one instrument. The DIB routes each channel to a point at which it is aligned with a mechanism to make a connection to a specific test point on the device under test.
A test system may have hundreds or thousands of channels, depending on the number of instruments installed in the test system. A device under test may have fewer pins than there are channels in a test system. Accordingly, a test process may also be made concurrent by testing multiple devices in parallel. In this case, multiple “sites” may be defined, with each site providing connections to one of the devices under test. The same test program may be run in parallel on each of the sites, effectively duplicating the pins of the device under test in each test site, with a corresponding duplication of required test resources.
For this concurrency to work, the DIB must be designed to connect channels to the sites such that at every step during a test flow an appropriate instrument is coupled to the each site to generate or measure a signal required on all pins in each site at that step in the test flow. As the number of pins and the number of types of signals that need to be generated and measured has increased, the time and complexity of designing a DIB has also increased. Though some tools are available to aid in this process, much of the design is still done manually by a test engineer figuring out how to assign test system channels to pins. In addition to the cost of the DIB design, the cost of delay for the device manufacturer can also be significant, because development of a test configuration can delay production of a device.